1. Field of the Invention
This invention relates to computer systems, and more particularly, to methods and apparatus for accelerating the transfer of data in a computer system utilizing multiple buses by guaranteeing access to retrying bus masters on a faster bus during a selected period.
2. History of the Prior Art
Historically, personal computers have utilized a single bus to transfer data between different internal components of the system. In personal computers using central processing units designed and manufactured by Intel Corporation of Santa Clara, Calif., such buses have typically been designed as either an Industry Standard Architecture (ISA) bus or an Expanded Industry Standard Architecture (EISA) bus. The ISA bus is a sixteen bit data bus while the EISA bus is thirty-two bits wide. Each of these buses functions at a frequency of eight megahertz. These bus widths and the rates at which each of these buses is capable of operating have been found limiting so there have been a number of attempts to increase bus speed.
One recently implemented method of increasing bus speed is to provide an additional, so called, "local bus" which is more closely associated with the central processor than either of the above-mentioned buses and which is capable of running at speeds that more closely approximate the speed at which the processor itself runs. Those system components which require faster operation than has been available using the slower buses (such as a graphics card for an output display device) are joined to this faster local bus. However, it is most desirable to be able to continue to utilize those components which were designed to operate with the older buses and which operate at a slower rate. In order to do this, the slower ISA or EISA bus is continued in essentially unchanged form; and those components which are able to tolerate longer access times are associated with the slower bus. It is then necessary to provide arrangements by which data may be transferred between all of the computer system components. This requires complicated interfacing arrangements. Although the theory behind using a local bus is good, many local bus designs have created conflicts in accessing components which actually slow the operation of the computer.
Intel Corporation has designed a new local bus which may be associated in a computer system with other buses such as an ISA bus or an EISA bus (which are hereinafter referred to broadly as secondary buses). This new local bus provides faster throughput of data for selected components of the system without the conflicts which may arise using other local bus systems. This new bus is referred to as the "peripheral component interconnect" (PCI) bus. A computer system using this PCI bus includes in addition to the physical PCI bus a first bridge circuit which provides the interface and controls the transfer of data among the PCI bus, the central processing unit, and main memory. A second bridge circuit is also provided as an interface between and a control for the transfer of data between the PCI bus and any secondary bus. Thus, the arrangement is such that components on the PCI bus transfer data to and receive data from main memory through the first bridge which joins to the central processor and to the main memory; while components on a secondary bus transfer and receive data through the second bridge and through the PCI bus for transfers with components on the PCI bus, and through the second and first bridges and the PCI bus for transfers with the central processor and the main memory.
Various designs of secondary bridges have been proposed. Specific embodiments of such bridges are described in detail in a publication entitled 82420/82430 PCIset, ISA and EISA Bridges, 1993, Intel Corporation. The design of these bridges is complicated by various factors. For example, each of the PCI and secondary buses is designed with controlling rules of operation (protocols) which must be adhered to in designing a bridge to connect the two disparate buses.
For example, the first bridge circuit which joins the central processing unit and main memory to the PCI bus is designed to buffer transfers of data so that a faster processor need not slow to the speed of the bus in transferring data. All bridge circuits joined to the PCI bus provide similar buffers. Buffering data write operations requires that data transfer operations be completed in a specific precise order to maintain data coherency. On the other hand, the secondary buses were designed without buffered transfers in mind. Once a bus master on one of these secondary buses gains access to the bus, it cannot be forced to relinquish its access. Certain of these secondary bus masters are required to complete operations on the secondary bus within a prescribed period of time and so must maintain their access and quickly complete their operations; failure to do so causes a non-recoverable system error. Consequently, if that access extends to the PCI bus (for example, to read from main memory), then the PCI bus will also be owned by the secondary bus master and will lose its speed advantage. Because of the different bus protocols, the transfer of data by a bridge has been found to be very complicated.
One problem which is inherent in the interfacing of the two buses into a single system is the problem of arbitrating for the buses. Since the PCI bus is designed to operate very rapidly, it is important that any operations on that bus take place without delay. For example, it is important that a PCI bus master not be required to wait on the PCI bus when it attempts to access the secondary bus for to do so would cause the PCI bus to lose the speed advantage for which it was designed. On the other hand, it is also necessary that components on the secondary bus have a fair chance of gaining access to the PCI bus and the various components on that bus such as main memory.
These last mentioned aims require unique circuitry be utilized for providing access to the PCI and secondary buses. Moreover, this circuitry must conform to the protocols and arbitration specifications of the individual buses in the system.